WLCSP package electromagnetic simulation (in collaboration with ST Microelectronics – Grenoble)

Wafer Level Chip Scale Package (WLCSP)

Simulation and optimization (via the use of electromagnetic simulation) of WLCSP packages (solder balls directly deposited on the chip). Learn more about WLCSP here

The goal is to work and propose solutions aimed at minimizing couplings and maximizing RF performance.

The circuits are RF products + STM32 microcontrollers, such as BLE, WiFi, etc.

Experience in EM 2.5D or ideally 3D simulation is required. The targeted simulation tool being Clarity from Cadence.

The internship is done in conjunction with the design and application teams.

The thesis require an internship at the ST Microelectronics premises in Grenoble.

For further information, contact Luigi Boccia